The present invention relates to a semiconductor device comprising a MIS transistor having a triple-well structure and to a fabrication method therefor. More particularly, it aims at increasing latch-up breakdown voltage.
As semiconductor devices have been increasingly miniaturized with recent advances in semiconductor fabrication technologies, the arrangement pitch of transistors has been reduced rapidly. As a result, the resistance of a well has increased prominently so that the lowering of latch-up breakdown voltage has presented a problem. Specifically, since an implantation angle (tilt angle) of about 7° is used in the ion implantation of an impurity for forming a well, an implant mask (resist) becomes a barrier in a well in the vicinity of the mask so that an amount of the implanted impurity is reduced and the impurity concentration is thereby lowered. The influence of the lowered concentration is negligible when the width of the well is large but, when the width of the well becomes smaller as a result of miniaturization, the ratio of a region in which the mask as the barrier lowers the impurity concentration to the entire well relatively increases. Consequently, the impurity concentration of the entire well prominently lowers and the well resistance increases so that the latch-up breakdown voltage lowers.
To prevent this, a so-called triple-well structure has been used in a memory such as a DRAM (dynamic random access memory), in which a P-type semiconductor substrate having a P-well region and an N-well region is provided with an N-type region having the peak of the impurity concentration thereof at a position deeper than each of the P-well region and the N-well region such that the resistance of the N-well region is reduced and the latch-up breakdown voltage is increased (see, e.g., Japanese Laid-Open Patent Publication No. HEI 9-55483).
FIG. 17 is a plan view showing an example of the layout of a conventional memory cell portion. FIG. 18 is a cross-sectional view taken along the line G-G′ of FIG. 17.
FIG. 19 is a cross-sectional view taken along the line Z-Z′ of FIG. 17.
As shown in FIGS. 17 to 19, a plurality of N-well regions 11 and a plurality of P-well regions 12 are formed to be alternately arranged, each extending from a surface of a P-type semiconductor substrate 10 toward the inside thereof. Between the N-well regions 11 and the P-well regions 12 in the surface portion of the P-type semiconductor substrate 10, there are provided isolations 14 having an STI (shallow trench isolation) structure, though they (isolations 104) are not shown in FIG. 17. In addition, a Deep-N-well region 13 is formed in a portion of the P-type semiconductor substrate 10 under the N-well regions 11 and the P-well regions 12 (i.e., a twin-well structure). The Deep-N-well region 13 is formed in an entire region under the twin-Well structure and at a depth which does not affect the surface concentration of the twin-well structure, thereby providing electrical connection between the individual N-well regions 11.
As also shown in FIGS. 17 to 19, an N-type MIS (metal-insulator semiconductor) transistor (e.g., NMOS (N-channel metal oxide semiconductor) transistor) 15 is formed on each of the P-well regions 12, while a P-type MIS transistor (e.g., PMOS (P-channel metal oxide semiconductor) transistor) 16 is formed on each of the N-well regions 11. Specifically, the N-type MIS transistors 15 is composed of: a gate oxide film 17 formed on each of the P-well regions 12; a gate electrode 18 formed on the gate oxide film 17; insulating sidewalls 19 formed on the side surfaces of the gate electrode 18; and N-type source/drain regions 20 formed in the surface portion of the P-well region 12. On the other hand, the P-type MIS transistor 16 is composed of: a gate oxide film 21 formed on each of the N-well regions 11; a gate electrode 22 formed on the gate oxide film 21; insulating sidewalls 23 formed on the side surfaces of the gate electrode 22; and P-type source/drain regions 24 formed in the surface portion of the N-well region 11.
For latch-up prevention in an SRAM (statistic random access memory), a method which uses an N-well/source structure, not a triple-well structure, in an SRAM memory cell and silicidizes a substrate surface is adopted in the invention disclosed in Japanese Laid-Open Patent Publication No. HEI 10-56082 to provide electrical connection between a P region and an N region and thereby reduce a contact area for a reduction in layout size.